沈天真
作者沈天真2021-05-05 10:41
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内存那些事儿----基础知识II

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接基础知识I

https://www.talkwithtrend.com/Article/255113

从上图可以看到从SDRAM到DDR3 SDRAM,核心频率并没有实质性进步,内存的核心频率一直在133MHz~200MHz之间徘徊。我们所看到的内存等效频率是在这个核心频率的基础上,通过各种技术手段放大出来的。之所以我们感觉内存在越来越快,就是这些技术手段在不断进步而已。

DDR SDRAM 延迟

DDR的延迟可通过一系列数字体现,如14-14-14-34,16-18-18-36等。这些数字表明内存进行某一操作所需的时钟脉冲数,数字越小,存储越快。

这些数字代表的操作如下:CL- tRCD – tRP – tRAS – CMD。

要理解这几个参数,需要知道内存被内部组织为一个矩阵,数据保存在行和列的交叉点。另外,还需要了解一个基本的读内存的流程如下:

首先是命令和地址信息输入,经过地址解码器分解成bank(段)和Word(字)选择,Word选择就是行选择,之后是对存储单元进行再存储(Restore)和预充电(Precharge)。然后是Column(列)选择,到此为止存储单元(cell)已经被定位。存储单元的数据被输出到内部数据总线(Internal Data Bus),最后通过输出电路输出数据。

下面是Wikipedia上对于这几个参数的解释。

CAS Latency (CL/tCAS)

列地址选通脉冲(CAS)延迟,是从处理器发出数据内存请求到内存开始返回数据间的时间。

Wikipedia: “The number of cycles between sending a column address to the memory and the beginning of the data in response. This is the number of cycles it takes to read the first bit of memory from a DRAM with the correct row already open. Unlike the other numbers, this is not a maximum, but an exact number that must be agreed on between the memory controller and the memory. CAS Latency is the most widely talked about and compared memory timing. ”

RAS to CAS Delay (tRCD)

行地址选通脉冲(RAS)到 CAS 的延迟,是激活行(RAS)和激活列(CAS)间的时间。

Wikipedia: “The minimum number of clock cycles required between opening a row of memory and accessing columns within it. The time to read the first bit of memory from a DRAM without an active row is tRCD + CL. RAS to CAS is one potential delay to read/writes. tRCD is the number of clock cycles it takes to open a row and access a column. If a request for data is made when there are no rows open, referred to as “page miss,” it will take at least tRCD + CL clock cycles for the CPU to receive the first bit of data in response.”

Row Precharge Time (tRP)

RAS 预充电时间,是禁用数据行接入和开始另一行数据接入间的时间。

Wikipedia: “The minimum number of clock cycles required between issuing the precharge command and opening the next row. The time to read the first bit of memory from a DRAM with the wrong row open is tRP + tRCD + CL. If the wrong row is open (“page miss”), it needs to be closed (precharged), then the next needs to be opened, then the column within the row needs to be accessed. This therefore takes tRP + tRCD + CL time.”

Row Active Time (tRAS):

激活预充电延时,是在启动下一次存储器接入前存储器必须等待的时间。

Wikipedia: “The minimum number of clock cycles required between a row active command and issuing the precharge command. This is the time needed to internally refresh the row, and overlaps with tRCD. In SDRAM modules, it is simply tRCD + CL. Otherwise, approximately equal to tRCD + 2×CL. Also known as Activate to Precharge Delay or Minimum RAS Active Time. The first equation (for SDRAM) is the relevant one here, but it should be more than that. We’ve seen multiple different “true” ways to calculate tRAS, but given the complexity of memory operations, good old trial and error remains the easiest. For example, we somehow booted with memory at 16-16-16-26, and that doesn’t make sense by anyone’s rules.”

Command Rate (CR/CMD/CPC/tCPD):

命令速率是存储芯片激活和向存储器发送第一个命令间的时间。有时,该值不会公布。它通常是 T1(1 个时钟速度)或 T2(2 个时钟速度)。

Wikipedia: “The amount of time, in cycles, between when a DRAM chip is selected and a command is executed. 2T CR can be very beneficial for stability with high memory clocks, or for 4-DIMM configurations.

Also known as Command Period. This will either be 1T or 2T on modern memory, with 1T being faster. Despite the unique -T notation, this is measured in clock cycles like the other timings. There’s generally a very small performance delta between the two options.”

上述几个参数中,最广泛使用的就是第一个参数 CL(CAS Latency)。

下图列出了一些常见内存的CL,如图中结论,可以看到DDR发展过程中,CL占用的时钟周期是越来越大的,但是由于每个时钟周期的时间在减少,所以实际的CL占用的时间是减少的。

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